1. Field of the Invention
The present invention relates to a PLL circuit and more particularly to a PLL circuit provided with a charge pump circuit.
2. Description of Related Art
In recent years, PLL (Phase Locked Loop) circuits have been used as an oscillation circuit incorporated into a semiconductor device in many cases. The PLL circuits control an oscillation frequency of an output signal to synchronize a phase of a reference signal with a phase of the output signal.
FIG. 7 is a block diagram of a general PLL circuit. As shown in FIG. 7, a PLL circuit 70 includes a phase comparing circuit (hereinafter referred to as “phase frequency comparator”) 71, a charge pump circuit 72, a loop filter 73, and a voltage-controlled oscillator 74.
The phase frequency comparator 71 compares a reference clock signal Fr with a feedback clock signal Fd obtained by feeding back an output clock signal Fout of the PLL circuit 70 and then outputs a voltage-up signal (hereinafter referred to as “UP signal”) and a voltage-down signal (hereinafter referred to as “DN signal”) for controlling the charge pump circuit 72. The charge pump circuit 72 outputs a current based on a pulse width difference between the UP signal and the DN signal and outputs a charge pump output voltage in accordance with an amount of the output current. This current is supplied in an inflow direction or outflow direction based on the pulse width difference between the UP signal and the DN signal under control. The loop filter 73 generates a voltage in accordance with a current output from the charge pump circuit 72. Further, the loop filter 73 filters out RF noise superimposed on the generated voltage. The voltage-controlled oscillator 74 sends out an output clock signal Fout having a frequency corresponding to a voltage generated through the loop filter 73. In addition, the output clock signal Fout is input to the phase frequency comparator 71 as the feedback clock signal Fd. In the PLL circuit 70 thus configured, the charge pump circuit 72 involves a parasitic capacitance (see FIG. 8). The parasitic capacitance leads to spiked noise in a current output from the charge pump circuit 72. Further, the spiked noise instantly modulates an oscillation frequency of an output clock signal Fout output from the voltage-controlled oscillator 74, which causes jitter. Japanese Unexamined Patent Application Publication No. 9-266443 describes a charge pump circuit to cancel the spiked noise caused by the parasitic capacitance.
FIG. 9 shows the charge pump circuit disclosed in Japanese Unexamined Patent Application Publication No. 9-266443. The charge pump circuit of FIG. 9 includes a main current control unit 91 and an overcurrent cancelling unit 92. In this case, the main current control unit 91 generates a spiked current Ip1 in accordance with a parasitic capacitance of a main current control unit 91 based on an input signal. On the other hand, the overcurrent cancelling unit 92 generates a spiked current Ip2 in opposite phase with the spiked current Ip1 output from the main current control unit 91 based on the same input signal as the signal input to the main current control unit 91. That is, the spiked current Ip1 output from the main current control unit 91 cancels out the spiked current Ip2 output from the overcurrent cancelling unit 92. In this way, spiked noise caused by the parasitic capacitance in the charge pump circuit 72 is cancelled out to thereby reduce jitter of the PLL circuit. In this case, the main current control unit 91 and the overcurrent cancelling unit 92 ideally have the same element characteristics.
However, according to the technique of Japanese Unexamined Patent Application Publication No. 9-266443, the same signal is input to the main current control unit 91and overcurrent cancelling unit 92, so if the main current control unit 91 and the overcurrent cancelling unit 92 have the same element characteristics, a predetermined current cannot be supplied from the overcurrent cancelling unit 92. That is, the charge pump circuit cannot perform an operation of outputting a current based on an input signal as the original operations, so it is impossible that the main current control unit 91 and the overcurrent cancelling unit 92 have the same element characteristics. Since the element characteristics are not equal as described above, the spiked noise cannot be cancelled out enough. Thus, the jitter of the PLL circuit cannot be reduced well.
As described above, in the charge pump circuit of the related art, spiked noise caused by a parasitic capacitance in the charge pump circuit cannot be cancelled out enough.